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****** EXTENDED SUBMISSION DEADLINE *******
Workshop on Hardware Acceleration of Biologically Inspired Algorithms
http://www.nabic-09.org/WorkShops_Topic.html
to be held in conjuction with The World Congress on Nature and Biologically
Inspired Computing (NABIC'09)
http://www.nabic-09.org
December 9th - 11th,
Coimbatore,
India
Preliminary call for papers
Overview
Traditionally, performance gains in computing were achieved by simply upgrading
hardware to take advantage of improved architectures and higher clock rates.
However, due to the power and thermal barriers faced by lead microprocessor
vendors, this trend has come to an abrupt halt. Today, attention has turned to
using specialized hardware to achieve performance gains. Popular hardware
accelerators include multi-core processors, Graphic Processing Units (GPUs),
and Field-Programmable Gate Arrays (FPGAs), just to name a few.
These accelerators aim to accelerate the run times of applications by providing
large amounts of parallel-computing resources. For example, NVIDIA's Tesla
architecture for GPU computing provides a fully programmable massively multi-
threaded chip with up to 128 scalar processor cores and is capable of
delivering hundreds of billions of operations per second. Xilinx's
Virtex-6 FPGA, on the other hand, offers over 680,000 logic cells, plus a
larger number of hard-wired macro blocks such as embedded memories
and processors.
As biologically inspired optimization algorithms are both common and
computationally expensive, they are excellent candidates for acceleration.
However, many biologically inspired algorithms, implemented in their
traditional form, lack the necessary structure to take full advantage of the
parallel resources available on these new architectures. Standard parallel
implementations are generally not sufficient to achieve high performance,
and naïve assumptions of linear performance scaling with the number of
cores are often wrong. This workshop is intended to bring together researchers
who are implementing biologically inspired algorithms on GPUs, FPGAs, multi-core,
and other relevant platforms, and who are addressing the challenges these
processes present. This session will provide a great opportunity for researchers
to discuss their approaches and exchange their expertise and solutions.
Topics of Interest
Submitted papers should be based upon, but not restricted to, the following topics:
* effective implementations of meta-heuristics, neural networks, and other relevant
algorithms on GPUs, FPGAs, and multi-core processors
* algorithm kernels for hardware implementations
* heterogeneous parallel computing platforms for biologically inspired algorithms
* cluster and grid deployment of biologically inspired algorithms
* strategies for minimizing communication cost between software and hardware
* strategies for exploiting on-board and on-chip memory
* strategies for mapping algorithms to appropriate hardware platforms
* experimental design methodologies for parallel implementations
* comparison of implementations on multiple hardware platforms
* new parallel search models and their implemenations in hardware/software
Important Dates and Deadlines
(Extended) Deadline for Paper Submission : July 30, 2009
Notification for Acceptance : August 14, 2009
Deadline for Camera Ready Manuscript : September 14, 2009
Submission Guidelines
Authors should submit an electronic version of papers using the "easychair" submission system
(http://www.easychair.org/conferences/?conf=nabic09).
The papers should be organized so as to accommodate abstract, introduction, state-of-the-art, objective,
used methodology, obtained results and references.
Please see a sample paper: http://www. softcomputing.net/synasc05.pdf
Submitted papers should be original and contain contributions of theoretical, experimental or application nature,
or be unique experience reports. Papers must be submitted within the stipulated time (June 19, 2009) and
electronic submission in PDF is required. The page limit for a full-length paper is 6 pages.
Short papers describing novel research visions, work-in-progress or less mature results are also welcome,
with the limit of 4 pages. All submissions should be in the IEEE 8.5 two-column format.
Papers should contain up to 5 keywords. Papers will be evaluated for originality, significance,
clarity, and soundness, and will be reviewed by at least three independent reviewers.
Accepted papers will be published by IEEE Computer Society Press.
Organizing Committee
Gary Grewal (Associate Professor)
Department of Computing and Information Science
University of Guelph
Guelph, Ontario, Canada
N1G 2W1
email: [log in to unmask]
phone: (519)-825-4120 x52630
fax: (519) 837-0323
Dilip Banerji (Professor)
Department of Computing and Information Science
University of Guelph
Guelph, Ontario, Canada
N1G 2W1
email: [log in to unmask]
phone: (519)-825-4120 x53005
fax: (519) 837-0323
Christian Fobel
Department of Computing and Information Science
University of Guelph
Guelph, Ontario, Canada
N1G 2W1
email: [log in to unmask]
phone: (519)-825-4120 x52483
fax: (519) 837-0323
Program Committee
* Kenneth Kent, University of New Brunswick (Canada)
* Sanaz Mostaghim, University of Karlsruhe (Germany)
* J. Ignacio Hidalgo, Complutense University of Madrid (Spain)
* Andrew Morton, University of Waterloo (Canada)
* Giandomenico Spezzano, ICAR-CNR (Italy)
* David McCaughan, SHARCNET (Canada)
* Brian Ross, Brock University (Canada)
* Paul Chow, University of Toronto (Canada)
* M. Balakrishnan, IIT, Delhi (India)
* Jose L. Risco, Complutense University of Madrid (Spain)
* Adrian Ludwin, Altera (Canada)
* Juan Lanchares, Complutense University of Madrid (Spain)
* William Gardner, University of Guelph (Canada)
* Mehdi Tahoori, Northeastern University (USA)
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