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CPHC-CONF  October 2008

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Subject:

Transactional Memory Seminar Series at University of Kent

From:

Richard Jones <[log in to unmask]>

Reply-To:

Richard Jones <[log in to unmask]>

Date:

Fri, 24 Oct 2008 17:40:45 +0100

Content-Type:

text/plain

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Parts/Attachments

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Dr Tony Hosking, University of Purdue, will be giving a series of  
three seminars on Transactional Memory at the University of Kent.  
These seminars are open to all. We also intend to make podcasts of  
these seminars available at

	http://www.cs.kent.ac.uk/research/groups/sys/seminars.html

The seminars will be held at 4pm in room SW101 in the Computing  
Laboratory.
Travel and campus maps can be found at http://www.kent.ac.uk/maps/.
A map of the Laboratory with the seminar room marked can be found at http://www.cs.kent.ac.uk/rooms/SW101.gif 
.

--
Hardware TM

Thursday 30th October 2008, 16:00 - 17:00

Transactional Memory has become a "hot" topic these days, as the now  
prevalent multi-core chips force revisiting support for parallel  
programming. I will survey some of the recent advances in TM, looking  
at both hardware and software solutions, and examining the gulf that  
still needs to be bridged between what hardware manufacturers plan to  
provide and what software abstractions will demand. The first of these  
talks will focus on hardware support, using the well-regarded  
Wisconsin LogTM architecture as a case study. The second talk  
(Thursday 6th November) will look at the programming abstractions that  
are being proposed for writing transactional programs, and how these  
abstractions map to the existing hardware, and where hybrid hardware/ 
software techniques are needed.

--

Language Extensions for Open Nested Transactions

Tuesday 4th November 2008, 16:00 - 17:00

We are seeing many proposals supporting atomic transactions in  
programming languages, software libraries, and hardware, some with and  
some without support for nested transactions. In the long run, it is  
important to support nesting, and to go beyond closed nesting to open  
nesting. I will argue as to the general form open nesting should take  
and why, namely that it is a property of classes (data types) not code  
regions, and must include support for programmed concurrency control  
as well as programmed rollback. I will also touch on the implications  
for software or hardware transactional memory in order to support open  
nesting of this kind. I will describe a concrete proposal for open  
nested transactions in Java. We argue that open nesting is most  
usefully seen as a way to express concurrency abstractions at  
different levels or granularities within (layered) data structures. To  
support this, we specify open nesting as a property of the class in  
Java, since the class is the principal data abstraction mechanism for  
Java programmers. Concurrency abstractions based on open nesting relax  
physical (memory-level) serializability while preserving abstract  
serializability. Abstract serializability is specified by the  
programmer in terms of abstract locks, which are associated with each  
of the operations (i.e., methods) operating at a given abstraction  
level (i.e., class), to specify the logical conflicts among  
concurrently executing operations. Abstract locks come with a  
predefined compatibility matrix used by the run-time system to mediate  
execution of these operations. We will describe the syntax and  
semantics of open nested classes for Java, and explore the power of  
the approach with an example. We will also point out possible pitfalls  
for programmers using open nesting, and discuss rules of thumb for  
programmers to use to avoid these problems.

--

Software TM

Thursday 6th November 2008, 16:00 - 17:00

Transactional Memory has become a "hot" topic these days, as the now  
prevalent multi-core chips force revisiting support for parallel  
programming. I will survey some of the recent advances in TM, looking  
at both hardware and software solutions, and examining the gulf that  
still needs to be bridged between what hardware manufacturers plan to  
provide and what software abstractions will demand. The first of these  
talks will focus on hardware support, using the well-regarded  
Wisconsin LogTM architecture as a case study. The second talk will  
look at the programming abstractions that are being proposed for  
writing transactional programs, and how these abstractions map to the  
existing hardware, and where hybrid hardware/software techniques are  
needed.

----

Antony Hosking received the Bachelor of Science inMathematical  
Sciences from the University of Adelaide, Australia, in May 1985, and  
the Master of Science inComputer Science from the University of  
Waikato, New Zealand, in April 1987. He continued his graduate studies  
at the University of Massachusetts, receiving the Ph.D. in Computer  
Science in February 1995. In January 1995,  Dr. Hosking was appointed  
to the faculty of Purdue University, where he now holds the rank of  
Associate Professor in Computer Science. His work is in the area of  
programming language design and implementation, with specific  
interests in database and persistent programming languages, object- 
oriented database systems, dynamic memory management, compiler  
optimization, and architectural support for programming languages and  
applications. Dr. Hosking is a Senior Member of the ACM and Member of  
the IEEE. Dr. Hosking serves on program and steering committees of  
several major international conferences, focusing on aspects of  
programming language design and implementation. Dr. Hosking received  
the Teaching for Tomorrow Award in 1998 as one of eight junior faculty  
at Purdue showing outstanding promise in teaching. In 2003 Dr. Hosking  
was elected one of the Top 10 Teachers in the College of Science by a  
poll of undergraduate students in the college.

We are grateful to the Engineering & Physical Sciences Research  
Council for supporting this series. Enquires about these seminars  
should be made to Richard Jones ([log in to unmask])

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