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FMNET  August 2016

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Subject:

Call for Participation: Automated Technology for Verification and Analysis (ATVA) 2016

From:

Takashi Kitamura <[log in to unmask]>

Reply-To:

Takashi Kitamura <[log in to unmask]>

Date:

Thu, 18 Aug 2016 13:52:07 +0900

Content-Type:

text/plain

Parts/Attachments:

Parts/Attachments

text/plain (109 lines)

----------------------------------------------------------------------
                  CALL FOR PARTICIPATION: ATVA 2016

                   14th International Symposium on
     Automated Technology for Verification and Analysis (ATVA) 2016

                 Chiba, Japan, October 17-20th, 2016

                   http://atva2016.gforge.inria.fr/
----------------------------------------------------------------------

The purpose of ATVA is to promote research on theoretical and practical
aspects of automated analysis, verification and synthesis by providing a
forum for interaction between the regional and the international research
communities and industry in the field. The previous events were held
in Taiwan - 2003-5, Beijing - 2006, Tokyo - 2007, Seoul - 2008, Macao -
2009, Singapore - 2010, Taiwan - 2011, Thiruvananthapuram - 2012, Hanoi -
2013, Sydney - 2014, and Shanghai - 2015.


Venue

Chiba, Japan

Main conference: Mitsui Garden Hotel

Tutorials: Chiba University, Nishi-Chiba campus (one station away from  
hotel)


Scope

* Formalisms for modeling hardware, software and embedded systems

* Specification and verification of finite-state, infinite-state and
   parameterized systems

* Program analysis and software verification

* Analysis and verification of hardware circuits, systems-on-chip and
   embedded systems

* Analysis of real-time, hybrid, priced/weighted and probabilistic systems

* Deductive, algorithmic, compositional, and abstraction/refinement
   techniques for analysis and verification

* Analytical techniques for safety, security, and dependability

* Testing and runtime analysis based on verification technology

* Analysis and verification of parallel and concurrent hardware/software
   systems

* Verification in industrial practice

* Applications and case studies


Keynotes (Oct. 17-19)

Masahiro Fujita: Unification of Synthesis and Verification in
                  Topologically Constrained Logic Design

Javier Esparza: From LTL to Limit-Deterministic Automata

Tevfik Bultan: Side Channel Analysis Using a Model Counting
                Constraint Solver and Symbolic Execution


Tutorials (Oct. 20)

Masahiro Fujita: Synthesizing and completely testing hardware based on
                  templates through small numbers of test patterns

Javier Esparza: Verification of population protocols

Tevfik Bultan: String Analysis for Vulnerability Detection and Repair


Important Dates:

Early registration: August 31 (Japan Standard Time)
Conference: October 17-20


Programme Committee Co-Chairs

Cyrille Artho (AIST, Japan and KTH, Sweden)
Axel Legay (INRIA, France)
Doron Peled (Bar Ilan University, Israel)


Publicity Chair

     Takashi Kitamura (AIST, Japan)


Local Chairs

     Mitsuharu Yamamoto (Chiba University, Japan)
     Yoshinori Tanabe (Tsurumi University, Japan)

-- 
Takashi KITAMURA
[log in to unmask]
http://staff.aist.go.jp/t.kitamura/
Tel: +81-72-751-9633, AIST internal: *33-272-79633

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