Hi John,
For the CMS tests we are using standard CMSSW with no special
compilations. Dell gave us plausible explanations as to why we were
seeing scaling problems. They also see problems when using highly tuned
compilers so the problems seem probably real. Although as I said
yesterday, we are not yet positive that is not a problem in CMSSW (we
may send our code to AMD to see if they can enlighten us). Given that
Dell don't see similar issues with the Sandy Bridge then we are pretty
desperate to get our mights and code on one to see for ourselves.
Best,
david
On 22/12/11 21:36, John Gordon wrote:
> Dave,Chris, do you expect these to be performant for pp codes as you never use specific compilers.
>
> David Colling<[log in to unmask]> wrote:
>
>
> We too have been doing tests with these but see significant scaling
> problems when running CMS codes. We are investigating further (or rather
> will do after Christmas).
>
> Talking to Dell they seemed unsurprised for what we are doing - but it
> is still very possible that the fault is at our end. They also said that
> they would not expect us to see similar problems with the Sandy Bridge
> and they would try to get us access to one to run more tests. It would
> then become a price performance issue (the Sandy Bridge will be more
> expensive/core).
>
> The problem from a GridPP point of view is that the Sandy Bridge is not
> due for release until February - good job that release dates never slip ;-)
>
> Best,
> david
>
> On 22/12/11 17:01, Christopher J.Walker wrote:
>> As we are looking at chips, I thought the following would be of interest:
>>
>> Chris
>>
>>
>> -------- Original Message --------
>> Subject: Re: [HPC-SIG] AMD Interlagos
>> Date: Wed, 21 Dec 2011 18:47:48 +0000
>> From: Parchment O.G.<[log in to unmask]>
>> Reply-To: HPC Special Interest Group discussion list
>> <[log in to unmask]>
>> To: [log in to unmask]
>>
>> Not sure if you have seen this already but it makes interesting reading,
>> www.hector.ac.uk/cse/reports/interlagos_whitepaper.pdf
>> Best Wishes
>> Oz
>>
>> -----Original Message-----
>> From: HPC Special Interest Group discussion list
>> [mailto:[log in to unmask]] On Behalf Of Dave Love
>> Sent: 21 December 2011 17:57
>> To: [log in to unmask]
>> Subject: Re: [HPC-SIG] AMD Interlagos
>>
>> michael<[log in to unmask]> writes:
>>
>>> AnandTech weren't giving glowing reports and implied recompilation
>>> (and yet to come software (scheduler?) advances) may be needed to get
>>> the most out of the HPC end of the chips such as 6282:
>>
>>> http://www.anandtech.com/show/5058/amds-opteron-interlagos-6200
>>
>> I'm puzzled why we should expect anything else for a new chip,
>> especially one with a new FP/vector architecture.
>>
>> By the way, apart from a suitable compiler, I suspect all bets are off
>> without careful attention to the increasingly complicated hardware
>> binding/affinity issues. Support for that will need to understand NUMA
>> node, which at least SGE didn't until very recently -- already relevant
>> for Magny Cours. See<http://www.open-mpi.org/projects/hwloc/> for
>> tools and library if necessary.
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